Many error detection and correction codes are known, including single and multiple parity bit codes, Hamming codes, and cyclic redundancy codes. As a general rule, the longer the string of bits used to store error checking information, the higher the probability that errors can be detected (and corrected if error correction is also employed). Further, the longer the string of data bits on which error detection is employed, the smaller the percentage increase in transmission time caused by appending a string of error checking information to the end of a data stream. Transmitting a long stream of error checking bits with a relatively short stream of data adds significantly to the total length of the transmission. However, transmitting a stream of error checking bits after a long stream of data causes a significant time delay before an error in the transmission can be detected. The longer the string of data bits to which error checking bits are appended, the longer the wait before discovering an error has occurred. In some applications it is important to minimize not only the percentage increase in the data stream used for error checking but also to minimize the waiting time for detecting any errors. Yet it may be necessary to assure with high reliability that no undetected errors have occurred.
One situation in which it is important to transmit data accurately and to detect quickly that an error has occurred is in the loading of memory cells which configure a logic cell array. Such logic cell arrays are explained more fully in U.S. Pat. Nos. 4,870,302 and 4,706,216, which are incorporated herein by reference. Such logic cell arrays are also described in Xilinx Data Book .COPYRGT.1989, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. The memory cells each control an interconnection, form part of a data table, select a logic function or part of a logic function, or otherwise control the configuration of the configurable logic array. This step of loading memory cells configures the logic array so that it takes on the function selected by a user. If any of the memory cells are not loaded with the proper logical value, the resultant configured logic array may not perform as intended. Therefore it is important that all data be loaded accurately.
To provide both high reliability and earlier error detection, prior art users have provided a nested hierarchy of error detection (and sometimes correction). For example a 9-bit byte protocol in which each byte includes 1 parity bit can be nested in a long chain using cyclic redundancy checking. Many other nested error checking methods have been used and can be imagined.